Very large scale integration semiconductor technologies have substantially increased the circuit density on a chip. Miniaturization of devices built in and on semiconductor substrates has led to ultra large scale integration with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With the improved integration, circuit elements such as memory cells experience electrical limitations resulting from their downsizing.
It is desirable to increase the integration density of memory cells on a memory chip by making the MOS transfer transistor and the storage capacitor which comprise a memory cell smaller. This has been particularly desirable with dynamic random access memory (DRAM) storage cells. However, the storage capacitor must be large enough to store sufficient charge for ensuring that data is correctly read from and written to the memory cell. Trench capacitors have been developed to increase the capacitance of the storage capacitor while permitting the integration density of memory cells to be increased.
FIGS 1A and 1B show a memory cell described in Nesbit et al., A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93-627-630, the contents of which are incorporated herein. Specifically, FIG. 1A illustrates a top-down view of a DRAM cell having a self-aligned buried strap and FIG. 1B is a cross-sectional view taken along I-I' of FIG. 1A. DRAM cell 50 includes a trench capacitor 55 and a transfer gate 60. Trench capacitor 55 includes a first N.sup.+ polysilicon fill 65, a second N.sup.+ polysilicon fill 67, and a collar oxide 71. Transfer gate 60 includes N-type source/drain regions 73 and 74 formed in a P-well 75 and a polysilicon gate 77 insulatively spaced from the channel between source/drain regions 73 and 74. A bit line contact 79 electrically connects source/drain region 73 to bit line 81. A shallow trench isolation (STI) arrangement 80 electrically isolates DRAM cell 50 from an adjacent memory cell and passing word line 92. A diffusion region 83 is formed to electrically connect third polysilicon fill 69 and source/drain region 74 of MOS transfer gate 60 by outdiffusing dopants from highly doped polysilicon fill in the storage trench into the P-well 75. Diffusion region 83 and third polysilicon fill 69 constitute a buried strap for connecting trench capacitor 55 to transfer gate 60.
One of the problems is that the resistance of the storage node (Rsn) poly becomes a much greater factor as technological advances are made to accommodate 256 Mbit, 1 GBit and larger DRAM cells. Consequently, with the shrinking design groundrule of high capacity DRAMs, the signal delay (tsd) in the sensing operation performed by a sense amplifier coupled to the bit line associated with a memory cell becomes increasingly large, thereby increasing memory cell access time to undesirable levels. For example, in a simulation of sensing delay versus storage node resistance for a 256 Mbit trench DRAM with a self-aligned BuriEd STrap (BEST) structure, it was found that the storage node resistance Rsn was 60 kOhms and the sensing signal delay tsn was 5.5 nanoseconds (ns). In the simulation for a 1 Gbit DRAM, the storage node resistance Rsn was 130 kOhms and the sensing signal delay tsn was 10 ns. The simulation was performed using both a lumped RC model and a distributed RC model, respectively shown in FIGS. 2A and 2B, with the following relations: Vto (transfer gate voltage)=0.75 volts@ Vpwell=0 volts; WL Vpp=3.5 volts; BL Vblh=1.8 volts; and "1" is data read. Using SPICE (circuit simulator) with the distributed and lumped RC models, the sensing delay (i.e., the delay time from the transfer gate being turned on to 90% signal output at the sense amplifier) was simulated. The results of the simulation are graphically represented in FIG. 2C which shows sensing delay vs. storage node resistance. The DRAM storage node resistance substantially increases between a 256 Mbit DRAM and a 1 Gbit DRAM. For a 1 Gbit DRAM, the diameter of the trench decreases as the design rule (feature size) decreases. However, the depth of the trench does not decrease so that a reasonable amount of storage capacitance (Cs) can be maintained. Thus, the deep trench polysilicon becomes much narrower, resulting in a storage node resistance substantially higher than the 256 Mbit DRAM.